The Lullaby-384 is an Open Hardware with Free Evaluation Firmware project. It is based on the high-performance STM32H7 MCU family (STM32H750VBT6). Featuring a no-FPGA architecture, the design focuses on pristine signal integrity and advanced clock management, utilizing specialized hardware blocks for galvanic isolation, flexible clock routing, and ultra-low jitter re-clocking.

The Lullaby-384 features full hardware support for audio oscillators operating at 512Fs or 1024Fs configurations, enabling highly versatile clock setups:

Master Mode: the board acts as the clock master, utilizing its on-board ultra-low-noise oscillators powered by a dedicated low-noise LDO to generate the Master Clock (MCLK). This clock is then sent across the isolation barrier to act as the downstream clock source for the audio system.

Slave Mode: The board acts as a clock slave, accepting an external MCLK input directly from an external high-precision clock source or DAC board.

To prevent ground loops and eliminate high-frequency digital noise, the design implements full galvanic isolation on both the I2S audio lines and control/auxiliary lines. The isolation stage utilizes high-speed digital isolators, such as the CA-IS3760HN and CA-IS3720LS (CA-IS3722LS for Slave mode).

The isolation barrier covers MCLK and I2S Lines - BCK, LRCLK and DATA, AUX/Control Lines - CP, D64, DSD ON and MUTE. Kindly note that some non-critical lines remain non-isolated - SPDIF OUT and the F0–F3 sample rate indicator lines.

In Master Mode, MCLK is routed through the CA-IS3720LS digital isolator. The "L" suffix (signifying a default LOW output state during unpowered or fault conditions) is mandatory because the CP (Cable Plugged) hardware signal is routed onto this IC along with MCLK. This ensures proper, safe logic levels when no USB cable is connected. Naturally, if the CP output is not used in your specific build, an isolator with a default HIGH state can be substituted. In Slave Mode, when MCLK is supplied from an external downstream master clock source, the signal is routed in the opposite direction through the IS3722LS isolator.

Galvanic Isolation Bypass (Non-Isolated Assembly Option). If galvanic isolation is not required, the entire isolation stage can be completely bypassed. By omitting the SOIC-8 and SOIC-16 digital isolator ICs, the board can be configured for direct, non-isolated operation using passive components (SMD 0603). Ground (GND) Link: Install zero-ohm jumpers across the designated ground isolation pads to tie the USB and DAC grounds together. Power Link (+3.3V): Install a 0603 size ferrite bead to bridge the +3.3V digital domains across the isolation barrier. Signal Lines (BCK, LRCK, DATA, MUTE etc.): Install 33 to 68 Ohm resistors.

By default, the digital audio stream output from the STM32H7’s SAI (Serial Audio Interface) peripheral goes through a hardware re-clocking stage based on ultra-fast 74AUP1G79 D-type flip-flops. This latches the isolated I2S lines directly with the clean master clock, completely bypassing any phase noise or jitter accumulated across the microcontrollers internal buses or the digital isolation barrier.

Hardware Re-Clocking Bypass: If you prefer to bypass the active re-clocking stage, the PCB provides dedicated 0402 SMD jumper pads. By omitting the 74AUP1G79 ICs and installing 0402 low-ohm resistors instead, the isolated I2S lines can be routed directly to the output connector. Frequency Limitations of Active Re-Clocking: It is important to note that while active re-clocking drastically minimizes jitter, it introduces strict timing constraints that limit the maximum achievable sample rate of the audio stream depending on your oscillator frequency:

DAC Chip Compatibility Warning (MCLK Selection): When choosing your master clock frequency, you must carefully verify the maximum supported MCLK/Fs ratio of your target DAC chip. Many popular modern DACs, such as the AK4493SEQ, along with older CS4398 or PCM1794, do not support a 1024Fs MCLK clock ratios. Therefore, please carefully evaluate your DAC's datasheet constraints to select the appropriate 512Fs or 1024Fs MCLK configuration and re-clock circuit for your hardware build.

To eliminate crosstalk, suppress digital switching noise, and ensure the lowest possible jitter for the audio oscillators, the Lullaby-384 features a highly sophisticated and flexible power delivery network. The board can be configured for various power scenarios depending on your chassis design and audiophile preferences. Once the main 5V rail is established, the power infrastructure branches into four independent, isolated voltage domains. This architecture strictly separates noisy digital processing blocks from the sensitive, noise-critical audio clocking and re-clocking circuitry.

External Power Input Options

On-Board Power Distribution & Ultra-Low-Noise LDOs

The Lullaby-384 supports a standard 4-pin I2C OLED (SSD1306) display with a 128x64 resolution, connected directly to the dedicated GND, VCC, SCL, and SDA pin header. The screen visualizes the streaming state of the system in real time, providing the following information:

PCM/DoP/DSD: Displays the current incoming audio stream sample rate and bit depth (e.g., 384000/32 for high-resolution 384 kHz / 32-bit playback).

FEr (Feedback Rate): Displays the current asynchronous feedback frequency calculated by the UAC2 stack to smoothly adjust the host PC's data flow rate.

DMA (FIFO Size): Shows the current configuration and block size of the hardware ring buffer (e.g., 2x 512 bytes), representing the active USB-to-SAI circular buffer handled by the internal DMA controller.

USB (Buffer Fill Level): Shows the exact real-time byte utilization of the primary 32kB USB audio buffer (e.g., 1136/32768 bytes) to monitor streaming stability. Under ideal conditions, the UAC2 feedback loop maintains the fill level slightly above the total DMA hardware buffer size (typically around 1100–1200 bytes for a 2x512 DMA setup) to provide a safe timing safety margin against USB bus latency.

CLOCK MODE & MCLK: Displays the active hardware clock topology - indicating whether the device is running in MASTER or SLAVE configuration, alongside the exact master clock frequency currently in use (e.g., 49.1520 MHz).

Project Footer: Displays the verified firmware project revision and design signature.

Main components are: STM32H750VBT6, USB3300, 74LVC157 (or 74HC157), 74LVC1G157, CA-IS3760HN, CA-IS3720LS (master mode) or CA-IS3722LS (slave mode). All resistors are 0402 and 0603 size, ferrite beads (BLMs) are 0603 and 0805 (USBPWR), capacitors are 0402, 0603, 0805.

LDO Noise Bypassing: For the 0402 footprints capacitors directly adjacent to the linear regulators (LDOs), use 10nF to 33nF values, in case these capacitors are required by the specific LDO for noise and ripple rejection improvement.

General Decoupling: All remaining decoupling capacitors, including the array located on the bottom side of the PCB, should be valued between 0.47 µF and 2.2 µF.

NB: To simplify the soldering process, all SMD capacitor footprints are marked with an internal dot, ferrite beads (BLMs) feature double lines, and resistors are left as empty outlines.

The Lullaby-384 is a community-focused project designed to give DIY audio enthusiasts total freedom in building high-quality USB UAC2 interface. To support the community, the core hardware assets - including the 2-layer PCB Gerber files and the bill of materials - along with a functional Evaluation Firmware are shared completely open and free for personal use.

You are fully permitted to download the Gerber files, order the PCBs from any manufacturer, source the components, and flash the free Evaluation Firmware onto your self-assembled board for private, non-commercial use.

Hardware Licensing (CC BY-NC 4.0): The physical PCB design, schematics, and bill of materials are distributed under the Creative Commons Attribution-NonCommercial 4.0 International License. Any commercial reproduction, manufacturing for sale, or cloning of the hardware design is strictly prohibited.

Evaluation Firmware Terms: The free Evaluation Firmware (provided in .hex format) is a pre-compiled binary licensed strictly for individual testing and private DIY builds. Bundling, reselling, or using this binary file for any commercial product is not permitted.