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Original DAC designs and schematics

Blue DAC Rev 2.2

  • DAC Chip (Firmware A) - PCM1794, PCM1798
  • DAC Chip (Firmware B) - PCM1792, PCM1795, PCM1796
  • Dynamic Range / THD+N (PCM1792, PCM1794) - 127dB / -108dB
  • Dynamic Range / THD+N (PCM1795, PCM1796, PCM1798) - 123dB / -106dB
  • Board size - 100×100 mm
  • PCM - up to 192kHz / 24bit, experimental up to 384 / 32 bit
  • DSD - up to DSD128, experimental up to DSD256
  • Control - MCU STM32F030C6
  • Power supply - DC 2x15V, DC 6V, DC 9V @ 0.1A
  • Inputs - USB-to-I2S interface
  • Features - Selectable digital filter Sharp or Slow, 16/24/32 bit mode selection, USB galvanic isolation, voltage drop monitoring
  • Display - SH1106 and SSD1306 I2C 128x64 modules supported with auto detect

Blue DAC Rev 2.2 - Project Overview

The Blue DAC Rev 2.2 is a modular, USB-transport-only DIY audio DAC built around Texas Instruments Burr-Brown PCM179x delta-sigma chips within a 100×100 mm footprint. It is managed by an STM32F030C6 microcontroller supporting I2C control, custom inputs handling, OLED display, digital filters selection, and bit depth options. The analog stage utilizes SOIC8 I/V op-amps, either DIP8 or SOIC8 patterns for LPF op-amp and provides a Class-A discrete buffer and anti-pop relays. Power distribution relies on dedicated linear regulation stages (compatible with external supplies such as Energy Ultra-Prime or Ultra-Quad) alongside an MCU-driven voltage drop detector for click-free shutdowns.

Digital Control & Firmware Architecture

An onboard STM32F030C6 microcontroller handles system management, drives the OLED display, and operates the PCM179x DAC chips. The firmware is split into two builds:

  • Firmware A: For hardware-controlled PCM1794 and PCM1798 variants (provided).
  • Firmware B: For software-controlled PCM1792, PCM1795, and PCM1796 variants (in development).

Key features include auto-detection of SSD1306/SH1106 OLED displays, real-time selection of bit depth (16/24/32-bit) and digital filters (Sharp/Slow), plus a 3-second Independent Watchdog timer (IWDG). For PCM1794/PCM1798 chips it provides only hardware pins configuration, while for PCM1792/PCM1795/PCM1796 chips full I2C control is intended.

Blue DAC Rev 2.2 PCB

Analog Stage

The analog section divides differential current outputs into dedicated stages:

  • I/V Stage: Uses high-performance SOIC-8 op-amps placed close to the DAC outputs, e.g. OPA1602 or OPA1612.
  • LPF Stage: Features a flexible combined SOIC-8 and DIP-8 footprint for op-amp rolling (e.g., OPA1612, LM4562, NE5532).
  • Discrete Out-of-Loop Buffer: Class-A discrete buffer follower (BC547 or similar NPN transistors and J-FET loads, e.g. SK170BL) placed outside the op-amp's global negative feedback loop.
  • Pop Protection: An MCU-controlled relay ensures silent track shifts, startup, and shutdown sequences.

Board Power Supply

Designed for external stabilized DC power rails such as the Energy Ultra-Prime or the Energy Ultra-Quad linear power supply units. The distribution includes:

  • PCM179x Analog Supply: DC 8V to 12V regulated via an LM7806 and three TPS7A2050 ultra-low-noise linear regulators.
  • Board Digital Supply: DC 6V to 9V, next routed through an LM1117-3.3 regulator to supply the +3.3V digital lines, external OLED display, and galvanic isolation circuitry.
  • I/V, LPF & Output Buffer: Dual-polar DC ±15V to ±18V fed into an M5230L regulator for a low-noise ±12V supply.

Voltage Drop Detector

The power-off sensing system relies on a hardware voltage divider connected to the incoming +9VD_NF rail using resistors R26, R28, and a resistor populated on the "VD2" diode footprint (supporting standard 0805 or 1206 packages).

  • PCB Layout: The PCB layout was originally designed to accommodate both digital (via the DD4D inverter stage) and analog voltage detector circuits. However, direct ADC-based monitoring proved to be significantly more reliable, utilizing only the V_DETECT_A line. To implement this ADC method, components R26, R28, C58, and the VD2 resistor pattern must be populated, while C56 and R34 are omitted.
  • Hardware Setup: The resistor values (e.g., 6.8kOhm for R26, 0 Ohm for R28, and 3.6kOhm for VD2) must be selected to step down the rail voltage to approximately 2.0V–3.0V at the MCU analog input pin. C58 value is 1nF.
  • Firmware Logic: At boot, the MCU checks the V_DETECT_A analog pin. If a valid voltage is detected, its value is stored in an internal variable, and the power-monitoring routine initializes immediately. If a sudden rail voltage drop occurs during operation, the MCU catches it instantly and drops the output relay to ensure a completely click-free shutdown.
  • Bypass Mode: If the ADC pin reads between 0V and 1V at startup (e.g., if R26 or R28 is missing), the system assumes the detector is disabled. The firmware skips the tracking routine and boots normally, though a minor pop noise may occur upon manual power-down.
Published on 09 November, 2026